As semiconductor technology advances beyond 130 nm and 90 nm technology towards 65 nm, 45 nm, 32 nm, and even beyond, the electrostatic discharge (ESD) protection for input/output (I/O) pads and their local clamps and supply clamps becomes more challenging. This is especially true for silicon-on-insulator (SOI) technology, which is expected to be preferable over bulk technology.
An ESD event refers to a phenomenon of electrical discharge of a current for a short duration during which a large amount of current is provided to a semiconductor structure. During an ESD event, an ESD protection device protects the semiconductor structure. An ideal ESD protection device operates like an open circuit during normal circuit operation, but operates like a short circuit which shunts current caused by the ESD event away from the protected semiconductor structure. While this ideal behavior is not possible in practical implementations, there are ESD protection devices which closely approximate this behavior.
Present-day ESD protection devices present a number of drawbacks. For example, some ESD protection circuits are unacceptable because they suffer from high leakage current and high capacitive loading.
Accordingly, it is desirable to provide an ESD protection device that exhibits low leakage and low capacitive loading. It also is desirable to provide an ESD protection device that enables a reduction in size of the device. In addition, it is desirable to provide a method for protecting a semiconductor structure from an ESD event using an improved ESD protection device. It is also desirable to provide a method for fabricating an ESD protection device which reduces or eliminates strict fabrication constraints associated with conventional Field Effect Diode (FED) fabrication methods. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.